B. Kuo, “Floating-Body Kink-Effect Related Capacitance Behavior of Nanometer PD SOI NMOS Gadgets” , EDMS , Taiwan

71. G. S. Lin and you may J. B. Kuo, “Fringing-Caused Thin-Channel-Effect (FINCE) Associated Capacitance Choices out-of Nanometer FD SOI NMOS Equipment Playing with Mesa-Separation Via 3d Simulation” , EDSM , Taiwan ,

72. J. B. Kuo, “Advancement of Bootstrap Approaches to Reduced-Voltage CMOS Electronic VLSI Circuits getting SOC Software” , IWSOC , Banff, Canada ,

P. Yang, “Entrance Misalignment Impression Related Capacitance Choices from an effective 100nm DG FD SOI NMOS Product with n+/p+ Poly Finest/Bottom Entrance” , ICSICT , Beijing, Asia

73. G. Y. Liu, Letter. C. Wang and you will J. B. Kuo, “Energy-Effective CMOS Higher-Stream Rider Circuit with the Subservient Adiabatic/Bootstrap (CAB) Way of Reasonable-Electricity TFT-Liquid crystal display Program Programs” , ISCAS , Kobe, The japanese ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Technology out of 100nm FD SOI CMOS Gizmos that have HfO2 High-k Gate Dielectric Offered Vertical and you will Fringing Displacement Outcomes” , HKEDSSC , Hong-kong ,

75. J. B. KUo, C. H. Hsu and you can C. P. Yang, “Gate-Misalignment Related Capacitance Choices off a beneficial 100nm DG SOI MOS Gadgets which have N+/p+ Top/Bottom Gate” , HKEDSSC , Hong-kong ,

76. G. Y. Liu, Letter. C. Wang and J. B. Kuo, “Energy-Efficient CMOS High-Load Rider Routine on Complementary Adiabatic/Bootstrap (CAB) Technique for Reduced-Stamina TFT-Liquid crystal display System Apps” , ISCAS , Kobe, The japanese ,

77. H. P. Chen and you will J. B. Kuo, “A beneficial 0.8V CMOS TSPC Adiabatic DCVS Reasoning Circuit to the Bootstrap Method getting Lowest-Strength VLSI” , ICECS , Israel ,

B. bravodate Kuo, “A novel 0

80. J. B. Kuo and you can H. P. Chen, “A minimal-Current CMOS Weight Rider to your Adiabatic and Bootstrap Approaches for Low-Power Program Applications” , MWSCAS , Hiroshima, The japanese ,

83. M. T. Lin, Age. C. Sunlight, and J. B. Kuo, “Asymmetric Entrance Misalignment Impact on Subthreshold Services DG SOI NMOS Gizmos Given Fringing Digital Field-effect” , Electron Devices and you may Question Symposium ,

84. J. B. Kuo, Age. C. Sunshine, and M. T. Lin, “Data from Door Misalignment Influence on the newest Endurance Voltage regarding Double-Entrance (DG) Ultrathin FD SOI NMOS Equipment Using a compact Design Considering Fringing Electronic Field effect” , IEEE Electron Gizmos to own Microwave and Optoelectronic Software ,

86. E. Shen and J. 8V BP-DTMOS Articles Addressable Thoughts Cellphone Circuit Produced by SOI-DTMOS Techniques” , IEEE Appointment to your Electron Equipment and Solid-state Circuits , Hong kong ,

87. P. C. Chen and you will J. B. Kuo, “ic Reason Routine Playing with an immediate Bootstrap (DB) Way of Lower-current CMOS VLSI” , Internationally Symposium to your Circuits and you will Options ,

89. J. B. Kuo and you will S. C. Lin, “Compact Breakdown Model to have PD SOI NMOS Products Offered BJT/MOS Impression Ionization getting Liven Circuits Simulator” , IEDMS , Taipei ,

ninety. J. B. Kuo and S. C. Lin, “Compact LDD/FD SOI CMOS Product Model Considering Opportunity Transport and you will Worry about Temperatures getting Liven Routine Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you may J. B. Kuo, “Fringing-Created Barrier Minimizing (FIBL) Results of 100nm FD SOI NMOS Equipment with high Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer” , IEEE SOI Conference Proc , Williamsburg ,

92. J. B. Kuo and you will S. C. Lin, “The fresh Fringing Electronic Field effect towards Short-Route Feeling Threshold Voltage of FD SOI NMOS Products that have LDD/Sidewall Oxide Spacer Structure” , Hong kong Electron Devices Meeting ,

93. C. L. Yang and you will J. B. Kuo, “High-Heat Quasi-Saturation Make of Higher-Voltage DMOS Electricity Gadgets” , Hong-kong Electron Gizmos Appointment ,

94. Elizabeth. Shen and you may J. B. Kuo, “0.8V CMOS Articles-Addressable-Thoughts (CAM) Phone Ciurcuit with a simple Tag-Compare Possibilities Playing with Vast majority PMOS Active-Tolerance (BP-DTMOS) Strategy Predicated on Standard CMOS Tech for Lowest-Voltage VLSI Assistance” , All over the world Symposium on the Circuits and you can Solutions (ISCAS) Process , Washington ,