B. Kuo, “Floating-Human anatomy Kink-Effect Relevant Capacitance Behavior out of Nanometer PD SOI NMOS Gizmos” , EDMS , Taiwan

71. G. S. Lin and you can J. B. Kuo, “Fringing-Triggered Slim-Channel-Impact (FINCE) Associated Capacitance Choices from Nanometer FD SOI NMOS Equipment Using Mesa-Separation Via three-dimensional Simulation” , EDSM , Taiwan ,

72. J. B. Kuo, “Development out-of Bootstrap Approaches to Reduced-Current CMOS Digital VLSI Circuits getting SOC Apps” , IWSOC , Banff, Canada ,

P. Yang, “Entrance Misalignment Perception Relevant Capacitance Behavior out of a beneficial 100nm DG FD SOI NMOS Equipment which have letter+/p+ Poly Best/Base Gate” , ICSICT , Beijing, Asia

73. G. Y. Liu, N. C. Wang and you can J. B. Kuo, “Energy-Efficient CMOS Highest-Stream Rider Circuit with the Subservient Adiabatic/Bootstrap (CAB) Way of Lowest-Stamina TFT-Liquid crystal display Program Software” , ISCAS , Kobe, The japanese ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you will K. W. Su, “CGS Capacitance Phenomenon off 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Straight and you may Fringing Displacement Effects” , HKEDSSC , Hong-kong ,

75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Related Capacitance Choices off good 100nm DG SOI MOS Products that have Letter+/p+ Top/Base Door” , HKEDSSC , Hong-kong ,

76. Canada ekteskapsbyrГҐ G. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Efficient CMOS Higher-Load Rider Circuit to your Complementary Adiabatic/Bootstrap (CAB) Technique for Lowest-Stamina TFT-Lcd Program Programs” , ISCAS , Kobe, Japan ,

77. H. P. Chen and you can J. B. Kuo, “A good 0.8V CMOS TSPC Adiabatic DCVS Reason Circuit to your Bootstrap Strategy having Lowest-Energy VLSI” , ICECS , Israel ,

B. Kuo, “A manuscript 0

80. J. B. Kuo and H. P. Chen, “A reduced-Voltage CMOS Load Rider into the Adiabatic and you will Bootstrap Suggestions for Low-Power Program Programs” , MWSCAS , Hiroshima, Japan ,

83. M. T. Lin, Elizabeth. C. Sunlight, and you can J. B. Kuo, “Asymmetric Entrance Misalignment Impact on Subthreshold Attributes DG SOI NMOS Products Given Fringing Electronic Field effect” , Electron Gizmos and you will Question Symposium ,

84. J. B. Kuo, Age. C. Sunshine, and Yards. T. Lin, “Data of Gate Misalignment Effect on the fresh new Endurance Current from Twice-Gate (DG) Ultrathin FD SOI NMOS Devices Having fun with a compact Design Considering Fringing Electronic Field-effect” , IEEE Electron Gizmos getting Microwave and you can Optoelectronic Programs ,

86. Age. Shen and you will J. 8V BP-DTMOS Stuff Addressable Thoughts Mobile Routine Produced by SOI-DTMOS Processes” , IEEE Conference toward Electron Equipment and you will Solid-state Circuits , Hong kong ,

87. P. C. Chen and you may J. B. Kuo, “ic Logic Circuit Using a direct Bootstrap (DB) Technique for Reasonable-voltage CMOS VLSI” , Around the world Symposium into the Circuits and Options ,

89. J. B. Kuo and you may S. C. Lin, “Compact Description Design having PD SOI NMOS Products Considering BJT/MOS Feeling Ionization having Liven Circuits Simulator” , IEDMS , Taipei ,

ninety. J. B. Kuo and you may S. C. Lin, “Compact LDD/FD SOI CMOS Equipment Model Offered Energy Transport and Notice Heating to own Spice Circuit Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you can J. B. Kuo, “Fringing-Created Barrier Minimizing (FIBL) Effects of 100nm FD SOI NMOS Gizmos with a high Permittivity Entrance Dielectrics and you will LDD/Sidewall Oxide Spacer” , IEEE SOI Appointment Proc , Williamsburg ,

ninety-five. J. B. Kuo and S. C. Lin, “Brand new Fringing Electronic Field-effect to your Brief-Station Impact Tolerance Voltage out of FD SOI NMOS Equipment with LDD/Sidewall Oxide Spacer Build” , Hong-kong Electron Products Meeting ,

93. C. L. Yang and J. B. Kuo, “High-Heat Quasi-Saturation Make of Large-Voltage DMOS Fuel Gizmos” , Hong kong Electron Equipment Conference ,

94. Age. Shen and you can J. B. Kuo, “0.8V CMOS Stuff-Addressable-Memory (CAM) Cell Ciurcuit with a simple Level-Contrast Features Playing with Majority PMOS Active-Threshold (BP-DTMOS) Strategy Based on Simple CMOS Tech getting Reasonable-Current VLSI Options” , Internationally Symposium on Circuits and you may Systems (ISCAS) Proceedings , Washington ,